CAPEC-696

This attack is a mix of techniques used in traditional Meltdown and Spectre attacks. It uses microarchitectural data leakage combined with code gadget abuse. Intel has identified that this attack is not applicable in scenarios where the OS and the VMM (Virtual Memory Manager) are both trusted. Because of this, Intel SGX is a prime target for this attack because it assumes that the OS or VMM may be malicious.

How the attack unfolds

1. Explore

   The attacker looks for a way in.

   1. [Survey target application and relevant OS shared code libraries] Adversary identifies vulnerable transient instruction sets and the code/function calls to trigger them as well as instruction sets or code fragments (gadgets) to perform attack. The adversary looks for code gadgets which will allow them to load an adversary-controlled value into trusted memory. They also look for code gadgets which might operate on this controlled value.

      1 technique

      • Utilize Disassembler and Debugger tools to examine and trace instruction set execution of source code and shared code libraries on a system.

2. Experiment

   They probe what they found.

   2. [Fill microarchitectural buffer with controlled value] The adversary will utilize the found code gadget from the previous step to load a value into a microarchitectural buffer.

      2 techniques

      • The adversary may choose the controlled value to be memory address of sensitive information that they want the system to access
      • The adversary may choose the controlled value to be the memory address of other code gadgets that they wish to execute by hijacking the control flow of the system

   3. [Set up instruction to page fault or microcode assist] The adversary must manipulate the system such that a page fault or microcode assist occurs when a valid instruction is run. If the instruction that fails is near where the adversary-controlled value was loaded, the system may forward this value from the microarchitectural buffer incorrectly.

      4 techniques

      • When targeting Intel SGX enclaves, adversaries that have privileges can manipulate PTEs to provoke page-fault exceptions or microcode assists.
      • When targeting Intel SGX enclaves, adversaries can indirectly revoke permissions for enclave code through the “mprotect” system call
      • An adversary can evict selected virtual memory pages using legacy interfaces or by increasing physical memory utilization
      • When attacking a Windows machine, wait until the OS clears the PTE accessed bit. When the page is next accessed, the CPU will always issue a microcode assist for re-setting this bit

3. Exploit

   They carry out the attack.

   4. [Operate on adversary-controlled data] Once the attack has been set up and the page fault or microcode assist occurs, the system operates on the adversary-controlled data.

      2 techniques

      • Influence the system to load sensitive information into microarchitectural state which can be read by the adversary using a code gadget.
      • Hijack execution by jumping to second stage gadgets found in the address space. By utilizing return-oriented programming, this can chain gadgets together and allow the adversary to execute a sequence of gadgets.

Prerequisites

• The adversary needs at least user execution access to a system and a maliciously crafted program/application/process with unprivileged code to misuse transient instruction set execution of the CPU.

• The CPU incorrectly transiently forwards values from microarchitectural buffers after faulting or assisted loads

• The adversary needs the ability to induce page faults or microcode assists on the target system.

• Code gadgets exist that allow the adversary to hijack transient execution and encode secrets into the microarchitectural state.

Skills required

• High skill

  Detailed knowledge on how various CPU architectures and microcode perform transient execution for various low-level assembly language code instructions/operations.

• High skill

  Detailed knowledge on compiled binaries and operating system shared libraries of instruction sequences, and layout of application and OS/Kernel address spaces for data leakage.

• High skill

  The ability to provoke faulting or assisted loads in legitimate execution.

Signs of an attack

• File Signatures for Malicious Software capable of abusing Transient Instruction Set Execution

Consequences

Mitigations

• Do not allow the forwarding of data resulting from a faulting or assisted instruction. Some current mitigations claim to zero out the forwarded data, but this mitigation still does not suffice.

• Insert explicit “lfence” speculation barriers in software before potentially faulting or assisted loads. This halts transient execution until all previous instructions have been executed and ensures that the architecturally correct value is forwarded.

Weaknesses it exploits

• CWE-1342 Information Exposure through Microarchitectural State after Transient Execution

Recent CVEs with these weaknesses

1. 6.8CVE-2026-187962026-09-07

   Any application that uses external QSPI flash for encrypted XIP on nRF5340 and relies on that encryption for confidentiality and/or integrity of the externally stored code. No specific nRF Connect SDK version is the root cau…

2. 6.5CVE-2023-287462024-03-14

   Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

3. 6.5CVE-2022-409822023-08-11

   Information exposure through microarchitectural state after transient execution in certain vector execution units for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

The newest records naming one of them. Each weakness's page lists them all.

Related attack patterns

Part of

• CAPEC-663 Exploitation of Transient Instruction Execution

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