CVE-2025-63384

6.5 mediumEPSS 0.3%

Medium (6.5) in chipsalliance rocketchip. EPSS 0.3% chance of exploitation in the next 30 days.

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

Severity

CVSS 3.1

6.5 medium

CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N

EPSS: 0.3% chance of exploitation in the next 30 days; higher than 25% of CVEs (scores of 2026-10-31)
CWE: CWE-266
Published: 2025-11-10
Modified: 2026-06-17
Record from: the NVD, synced 2026-10-19

Affected

chipsalliance:rocketchip

References

https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET
https://github.com/chipsalliance/rocket-chip.git

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