CVE-2024-24853

7.3 highEPSS 0.2%

High (7.3). EPSS 0.2% chance of exploitation in the next 30 days.

Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

Severity

CVSS 4.0

7.3 high

CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H

CVSS 3.1

7.2 high

CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H

EPSS: 0.2% chance of exploitation in the next 30 days; higher than 14% of CVEs (scores of 2026-10-31)
CWE: CWE-696
Published: 2024-08-14
Modified: 2026-06-17
Record from: the NVD, synced 2026-10-19

References

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html

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